荔枝派Nano调试心得

suniv-f1c100s.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR X11) /* * Copyright 2018 Icenowy Zheng 
   
     * Copyright 2018 Mesih Kilinc 
    
      */ 
     
    #include  
     #include  
     / { 
    #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; clocks { 
    osc24M: clk-24M { 
    #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <>; clock-output-names = "osc24M"; }; osc32k: clk-32k { 
    #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; clock-output-names = "osc32k"; }; }; cpus { 
    cpu { 
    compatible = "arm,arm926ej-s"; device_type = "cpu"; }; }; soc { 
    compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; sram-controller@1c00000 { 
    compatible = "allwinner,suniv-f1c100s-system-control", "allwinner,sun4i-a10-system-control"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; ranges; sram_d: sram@10000 { 
    compatible = "mmio-sram"; reg = <0x00010000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00010000 0x1000>; otg_sram: sram-section@0 { 
    compatible = "allwinner,suniv-f1c100s-sram-d", "allwinner,sun4i-a10-sram-d"; reg = <0x0000 0x1000>; status = "disabled"; }; }; }; ccu: clock@1c20000 { 
    compatible = "allwinner,suniv-f1c100s-ccu"; reg = <0x01c20000 0x400>; clocks = <&osc24M>, <&osc32k>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; }; intc: interrupt-controller@1c20400 { 
    compatible = "allwinner,suniv-f1c100s-ic"; reg = <0x01c20400 0x400>; interrupt-controller; #interrupt-cells = <1>; }; pio: pinctrl@1c20800 { 
    compatible = "allwinner,suniv-f1c100s-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <38>, <39>, <40>; clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; #gpio-cells = <3>; uart0_pe_pins: uart0-pe-pins { 
    pins = "PE0", "PE1"; function = "uart0"; }; mmc0_pins: mmc0-pins { 
    pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; }; spi1_pins: spi1-pins{ 
    pins="PA2","PA0","PA3","PA1"; function = "spi1"; }; }; timer@1c20c00 { 
    compatible = "allwinner,suniv-f1c100s-timer"; reg = <0x01c20c00 0x90>; interrupts = <13>; clocks = <&osc24M>; }; wdt: watchdog@1c20ca0 { 
    compatible = "allwinner,suniv-f1c100s-wdt", "allwinner,sun4i-a10-wdt"; reg = <0x01c20ca0 0x20>; }; uart0: serial@1c25000 { 
    compatible = "snps,dw-apb-uart"; reg = <0x01c25000 0x400>; interrupts = <1>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu 38>; resets = <&ccu 24>; status = "disabled"; }; uart1: serial@1c25400 { 
    compatible = "snps,dw-apb-uart"; reg = <0x01c25400 0x400>; interrupts = <2>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu 39>; resets = <&ccu 25>; status = "disabled"; }; uart2: serial@1c25800 { 
    compatible = "snps,dw-apb-uart"; reg = <0x01c25800 0x400>; interrupts = <3>; reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu 40>; resets = <&ccu 26>; status = "disabled"; }; mmc0: mmc@1c0f000 { 
    compatible = "allwinner,suniv-f1c100s-mmc", "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>, <&ccu CLK_MMC0_OUTPUT>, <&ccu CLK_MMC0_SAMPLE>; clock-names = "ahb","mmc","output","sample"; resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = <23>; pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; spi1:spi@1c06000 { 
    compatible = "allwinner,suniv-spi", "allwinner,sun8i-h3-spi"; reg = <0x1c06000 0x1000>; interrupts = <0xb>; clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>; clock-names = "ahb", "mod"; resets = <&ccu RST_BUS_SPI1>; status = "okay"; #address-cells = <1>; #size-cells = <0>; bias-pull-up; pinctrl-names = "default"; pinctrl-0 = <&spi1_pins>; }; dma: dma-controller@1c02000 { 
    compatible = "allwinner,suniv-f1c100s-dma"; reg = <0x01c02000 0x1000>; interrupts = <18>; clocks = <&ccu CLK_BUS_DMA>; resets = <&ccu RST_BUS_DMA>; #dma-cells = <2>; }; }; }; 

suniv-f1c100s-licheepi-nano.dts

// SPDX-License-Identifier: (GPL-2.0+ OR X11) /* * Copyright 2018 Icenowy Zheng 
   
     */ 
    /dts-v1/; #include "suniv-f1c100s.dtsi" #include  
     #include  
     / { 
    model = "Lichee Pi Nano"; compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; aliases { 
    serial0 = &uart0; }; chosen { 
    stdout-path = "serial0:n8"; }; reg_vcc3v3: vcc3v3 { 
    compatible = "regulator-fixed"; regulator-name = "vcc3v3"; regulator-min-microvolt = <>; regulator-max-microvolt = <>; }; }; &uart0 { 
    pinctrl-names = "default"; pinctrl-0 = <&uart0_pe_pins>; status = "okay"; }; &mmc0 { 
    vmmc-supply = <&reg_vcc3v3>; bus-width = <4>; broken-cd; status = "okay"; };