vmi运行流程简图_申请强制执行后多久执行

vmi运行流程简图_申请强制执行后多久执行`vmm_test_begin(testcase_name,vmm_env,”TestCaseNameString”) `vmm_test_env(testcase_name)

大家好,又见面了,我是你们的朋友全栈君。如果您正在找激活码,请点击查看最新教程,关注关注公众号 “全栈程序员社区” 获取激活教程,可能之前旧版本教程已经失效.最新Idea2022.1教程亲测有效,一键激活。

Jetbrains全系列IDE使用 1年只要46元 售后保障 童叟无欺

`vmm_test_begin(testcase_name,vmm_env,“Test Case Name String”) ;

env.build() ;

env.reset_dut() ;

env.start() ;

env.wait_for_end() ;

env.report() ;

`vmm_test_end(testcase_name);



参考文献:http://www.testbench.in/VM_09_VMM_TEST.html

vmm_test is introduced in vmm 1.1. 

To know the vmm version which you are using, use this command 
vcs -R -sverilog -ntb_opts dtm 
+incdir+$VMM_HOME/sv $VMM_HOME/sv/vmm_versions.sv 


vmm_test is used for compiling all the testcases in one compilation. The simulation of each testcase is done individually. Traditionally for each testcase, compile and simulation are done per testcase file. With this new approach, which dose compilation only once, will save lot of cup. 


Generally each testcase can be divided into two parts. 


(S)Procedural code part. 


The procedural code part (like passing the above new constrained transaction definition to some atomic generator, calling the env methods etc) has to be defined between these macros. vmm provides 2 macros to define testcase procedural part. 


`vmm_test_begin(testcase_name,vmm_env,“Test Case Name String”) 
`vmm_test_env(testcase_name) 

(S)Declarative code part. 


The declarative part( like new constrained transacting definition) is defined outside these macros. 



Writing A Testcase 



Let us see an example of writing a testcase. 
Inside the testcase, we will define a new transaction and pass this transaction to the atomic generator. 



(S) Declarative part: 


1) Define all the declarative code. 


class constrained_tran extends pcie_transaction; 

// Add some constraints 
// Change some method definitions 

end class 


2) Define a handle to the above object. 


constrained_tran c_tran_obj; 

(S) Procedural part: 


Use a `vmm_test_begin . There are 3 arguments to macro. 

vmi运行流程简图_申请强制执行后多久执行 
The first argument is the name of the testcase class and will also be used as the name of the testcase in the global testcase registry. 
vmi运行流程简图_申请强制执行后多久执行 
The second argument is the name of the environment class that will be used to execute the testcase. A data member of that type named “env” will be defined and assigned, ready to be used. 
vmi运行流程简图_申请强制执行后多久执行 
The third argument is a string documenting the purpose of the test. 



`vmm_test_begin(test_1,vmm_env,“Test_1”) 


In this testcase, we want to pass the c_tran_obj object. The steps t pass the c_tran_obj as per the vmm_env is 


env.build(); 
c_tran_obj = new(” “); 
env.atomic_gen.randomized_obj = c_tran_obj; 


Start the vmm_env execution. 


env.run(); 


Now use `vmm_test_end to define the end of the testcase. The argument to this is the testcase name. 


`vmm_test_end(test_1) 


Following is the full testcase source code which we discussed above. 
(S) Testcase source code 

class constrained_tran extends pcie_transaction; 

end class 

constrained_tran c_tran_obj 

`vmm_test_begin(test_1,vmm_env,“Test_1”) 
$display(” Start of Testcase : Test_1 “); 
env.build(); 
c_tran_obj = new(” “); 
env.atomic_gen.randomized_obj = c_tran_obj; 
env.run(); 
$display(” End of Testcase : Test_1 “); 
`vmm_test_end(test_1) 




Like this you can write many testcases in separate file or single file. 


Example Of Using Vmm_test 



Now we will implement 3 simple testcases and a main testcase which will be used for selecting any one of the 3 testcases. 


(S) testcase_1 


Write this testcase in a testcase_1.sv file 



// Define all the declarative code hear. I done have anything to show you. 
// 
// class constrained_tran extends pcie_transaction; 
// 
// end class 
// 
// constrained_tran c_tran_obj 

`vmm_test_begin(test_1,vmm_env,“Test_1”) 
$display(” Start of Testcase : Test_1 “); 
// This is procedural part. You can call build method. 
env.build(); 

// You can pass the above created transaction to atomic gen. 
// c_tran_obj = new(” “); 
// env.atomic_gen.randomized_obj = c_tran_obj; 
// 
// 

env.run(); 
$display(” End of Testcase : Test_1 “); 
`vmm_test_end(test_1) 

(S)testcase_2 


Write this testcase in a testcase_2.sv file 



`vmm_test_begin(test_2,vmm_env,“Test_2”) 
$display(” Start of Testcase : Test_2 “); 
// Do something like this …. 
env.build(); 
// like this …. 
env.run(); 
$display(” End of Testcase : Test_2 “); 
`vmm_test_end(test_2) 

(S)testcase_3 


Write this testcase in a testcase_3.sv file 



`vmm_test_begin(test_3,vmm_env,“Test_3”) 
$display(” Start of Testcase : Test_3 “); 
// Do something like this …. 
env.build(); 
// like this …. 
env.run(); 
$display(” End of Testcase : Test_3 “); 
`vmm_test_end(test_3) 

(S)main testcase 


Now we will write the main testcase. This doesn’t have any test scenario, it is only used for handling the above 3 testcases. 


This should be written in program block. 

1) First include all the above testcases inside the program block. 


`include “testcase_1.sv” 
`include “testcase_2.sv” 
`include “testcase_3.sv” 


2) Define env class object. 


vmm_env env = new(); 


As I dont have a custom env class to show, I used vmm_env. You can use your custom defined env. 

3) In the initial block call the run() method of vmm_test_registry class and pass the above env object as argument. This run method of vmm_test_registry is a static method, so there is no need to create an object of this class. 


vmm_test_registry::run(env); 


(S) Main testcase source code 

`include “vmm.sv” 
program main(); 

`include “testcase_1.sv” 
`include “testcase_2.sv” 
`include “testcase_3.sv” 

vmm_env env; 

initial 
begin 
$display(” START OF TEST CASE “); 
env = new(); 
vmm_test_registry::run(env); 
$display(” START OF TEST CASE “); 
end 


endprogram 



Now compile the above code using command. 

vcs -sverilog main_testcase.sv +incdir+$VMM_HOME/sv 

Now simulate the above compiled code. 

To simulate , just do ./simv and see the log. 
You can see the list of the testcases. This simulation will not ececute any testcase. 


(S)LOG 

START OF TEST CASE 
*FATAL*[FAILURE] on vmm_test_registry(class) at 0: 
No test was selected at runtime using +vmm_test=<test>. 
Available tests are: 
0) Default : Default testcase that simply calls env::run() 
1) test_1 : Test_1 
2) test_2 : Test_2 
3) test_3 : Test_3 



To run testcase_1 use ./simv +vmm_test=test_1 


(S)LOG 

START OF TEST CASE 
Normal[NOTE] on vmm_test_registry(class) at 0: 
Running test “test_1″… 
Start of Testcase : Test_1 
Simulation PASSED on /./ (/./) at 0 (0 warnings, 0 demoted errors & 0 demoted warnings) 
End of Testcase : Test_1 
START OF TEST CASE 



Simillarly to run testcase_2 ./simv +vmm_test=test_2 


(S)LOG 

START OF TEST CASE 
Normal[NOTE] on vmm_test_registry(class) at 0: 
Running test “test_2″… 
Start of Testcase : Test_2 
Simulation PASSED on /./ (/./) at 0 (0 warnings, 0 demoted errors & 0 demoted warnings) 
End of Testcase : Test_2 
START OF TEST CASE 



You can also call the Default testcase, which just calls the env::run() 

./simv +vmm_test=Default 


(S)LOG 

START OF TEST CASE 
Normal[NOTE] on vmm_test_registry(class) at 0: 
Running test “Default”… 
Simulation PASSED on /./ (/./) at 0 (0 warnings, 0 demoted errors & 0 demoted warnings) 
START OF TEST CASE 




(S) Download the source code 


vmm_test.tar 
Browse the code in vmm_test.tar 



(S) Command to compile 


vcs -sverilog -ntb_opts dtm +incdir+$VMM_HOME/sv main_testcase.sv 


(S) Commands to simulate testcases 


./simv 
./simv +vmm_test=Default 
./simv +vmm_test=test_1 
./simv +vmm_test=test_2 
./simv +vmm_test=test_3 

版权声明:本文内容由互联网用户自发贡献,该文观点仅代表作者本人。本站仅提供信息存储空间服务,不拥有所有权,不承担相关法律责任。如发现本站有涉嫌侵权/违法违规的内容, 请联系我们举报,一经查实,本站将立刻删除。

发布者:全栈程序员-站长,转载请注明出处:https://javaforall.net/190631.html原文链接:https://javaforall.net

(0)
全栈程序员-站长的头像全栈程序员-站长


相关推荐

  • springboot集成CAS单点登录客户端

    springboot集成CAS单点登录客户端1.springboot项目pom.xml中添加cas客户端依赖包<dependency><groupId>org.jasig.cas.client</groupId><artifactId>cas-client-core</artifactId><version>3.5.0</…

    2022年5月15日
    30
  • Fluent UDF【1】:简介

    Fluent UDF【1】:简介前面基本完成了动网格专题的发布,不过还是有一些内容并没有更新进去,比如说incylinder、接触检测、2.5D网格重构等。不过这些都是小技巧,写起来挺麻烦,以后有时间再通过案例视频的方式讲解好了。

    2022年7月2日
    28
  • 庆祝kkkbo出道!

    庆祝kkkbo出道!希望学编程有始有终,不做弱者,不做断者-常思华联兴之日子,多念华联兴之饭菜,忆图思苦,勉励自身。

    2022年7月3日
    41
  • 自监督学习之对比学习

    自监督学习之对比学习对比学习一般是自监督学习的一种方式什么是自监督学习自监督学习主要是利用辅助任务(pretext)从大规模的无监督数据中挖掘自身的监督信息,通过这种构造的监督信息对网络进行训练,从而可以学习到对下游任务有价值的表征。(也就是说自监督学习的监督信息不是人工标注的,而是算法在大规模无监督数据中自动构造监督信息,来进行监督学习或训练。因此,大多数时候,我们称之为无监督预训练方法或无监督学习方法,严格上讲,他应该叫自监督学习)。  原文作者:自编码器个人认为可以算作无监督学习,也可以算作自监督学.

    2022年9月14日
    0
  • 1024代理服务器网站,1024hgc.com服务器iP「建议收藏」

    2021-07-26—–2021-08-10172.67.24.1612021-07-26—–2021-08-10104.22.46.962021-07-26—–2021-08-10104.22.47.962021-03-25—–2021-07-26104.26.3.652021-03-25—–2021-07-26104.26.2.652021-03-25—–2…

    2022年4月9日
    96
  • 自动控制原理哈工大课后答案_控制系统的数学模型答案

    自动控制原理哈工大课后答案_控制系统的数学模型答案计算机控制系统大作业,简析冯诺依曼结构和哈佛结构异同浅析冯诺依曼结构与哈佛结构摘要:本文简要介绍了冯诺依曼结构与哈佛结构,将两者原理及应用情况进行了对比分析,并对计算机组成发展趋势做了简单预测。关键词:计算机系统结构冯诺依曼结构哈佛结构1冯诺依曼结构与哈佛结构1.1冯诺依曼结构冯诺依曼结构(VonNeumannarchitecture),也称普林斯顿结构,它把程序本身当作数据来对待,程…

    2022年9月28日
    0

发表回复

您的邮箱地址不会被公开。 必填项已用 * 标注

关注全栈程序员社区公众号