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通过oddr把两路单端的数据合并到一路上输出 上下沿同时输出数据 上沿输出a路下沿输出b路 如果两路输入信号一路恒定为1，一路恒定为0，那么输出的信号实际上就是输入的时钟信号
ODDR
The ODDR primitive is a dedicated output registers to transmit dual data rate (DDR) signals from Virtex-4 FPGAs. Unlike previous generations of Xilinx FPGAs, ODDR primitive’s interface with the FPGA fabric is not limited to opposite edges. ODDR is available with modes that allow data to be presented from the FPGA fabric at the same clock edge. This feature allows designers to avoid additional timing complexities and CLB usage. In addition, IDDR will work in conjunction with Select I/O features of Xilinx Virtex-4 architecture.
ODDR Ports (Detailed Description)
Q – Data Output (DDR)
These pins are the ODDR output that connects to the IOB pad.
C – Clock Input Port
The C pin represents the clock input pin.
CE – Clock Enable Port
When asserted LOW, this port disables the output clock at port O.
D1 – D2 – Data Input
This pin is where the DDR data is presented into the ODDR module. This pin connects to the IOB pad.
R – Reset
Asynchronous reset pin. Reset is assert HIGH
R – Reset
Depends on how SRTYPE is set. See “Available Attributes” table below.
ODDR Modes
The following section describes the functionality of various modes of ODDR. These modes are set by the DDR_CLK_EDGE attribute.
OPPOSITE_EDGE
In the OPPOSITE_EDGE mode, data transmit interface uses the classic DDR methodology. Given a data and clock at pin D1-2 and C respectively, D1 will be sampled at every positive edge of clock C, and D2 will be sampled at every negative edge of clock C. Q changes every clock edge.
SAME_EDGE
In the SAME_EDGE mode, data is still transmitted by opposite edges of clock C. However, both register are clocked with positive clock edge C and an extra register has been placed in front of the D2 input data register. The extra register is clocked with negative clock edge of clock signal C. Using this feature, DDR data can now be presented into the ODDR at the same clock edge.
Port List and Definitions
|
Name
|
Type
|
Width
|
Function
|
|---|---|---|---|
|
Q
|
Output
|
1
|
Data Output (DDR)
|
|
C
|
Input
|
1
|
Clock input
|
|
CE
|
Input
|
1
|
Clock enable input
|
|
D1 – D2
|
Input (each)
|
1
|
Data Input
|
|
R
|
Input
|
1
|
Reset
|
|
S
|
Input
|
1
|
Set
|
Available Attributes
|
Name
|
Description
|
Possible Values
|
|---|---|---|
|
DDR_CLK_EDGE
|
DDR clock mode recovery mode selection
|
OPPOSITE_EDGE, SAME_EDGE
|
|
INIT
|
Q initialization value
|
1’b0, 1’b1
|
|
SRTYPE
|
Set/Reset type selection
|
ASYNC, SYNC
|
VHDL Instantiation Template
-- ODDR: Output Double Data Rate Output Register with Set, Reset -- and Clock Enable. Virtex-4 -- Xilinx HDL Libraries Guide version 6.3i ODDR_inst : ODDR generic map ( DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '0', -- Initial value of Q: '0' or '1' SRTYPE => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC" port map ( Q => Q, -- 1-bit DDR output C => C, -- 1-bit clock input CE => CE, -- 1-bit clock enable input D1 => D1, -- 1-bit data input (positive edge) D2 => D2, -- 1-bit data input (negative edge) R => R, -- 1-bit reset S => S -- 1-bit set ); -- End of ODDR_inst instantiation Verilog Instantiation Template
// ODDR: Output Double Data Rate Output Register with Set, Reset // and Clock Enable. Virtex-4 // Xilinx HDL Libraries Guide version 6.3i ODDR ODDR_inst ( .Q(Q), // 1-bit DDR output .C(C), // 1-bit clock input .CE(CE), // 1-bit clock enable input .D1(D1), // 1-bit data input (positive edge) .D2(D2), // 1-bit data input (negative edge) .R(R), // 1-bit reset .S(S) // 1-bit set ); // The following defparams specify the behavior of the ODDR // component. If the instance name is changed, that // change needs to be reflected in the defparam statements. defparam ODDR_inst.DDR_CLK_EDGE = "OPPOSITE_EDGE"; // "OPPOSITE_EDGE" or "SAME_EDGE" defparam ODDR_inst.INIT = 1'b0; // Initial value of Q: 1'b0 or 1'b1 defparam ODDR_inst.SRTYPE = "SYNC"; // Set/Reset type: "SYNC" or "ASYNC" // End of ODDR_inst instantiation
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