about aarch64

Focus on high performance
Exception levels instead of different modes
virtualisation support built-in
32 bit fixed length instruction
more registers
divide instruction
compare & jump instruction
support for aarch32

difference towards aarch32

no thumb mode
only a handful conditionally executing instruction
no more coprocessor
beware PC relative addressing doesn’t have an offset anymore
31 general purpose registers.1 special purpose
no store/load multiple registers(only pairs)

aarch64 registers

registers   special description
SP/ZR               Stack pointor/Zero register
30          LR      Link register
29          FP      Frame pointer
19~28              stored/restored by callee
18                  platforem specific register
17                  inter procedure call 1 16 inter procedure call 2 9~15 scratch registers 8 indirect result(pointer to sturct) 0~7 parameters & results

registers can be accessed as 32/64 bit

X0~30 for 64 bit
W0~30 for 32 bit
Also available
V0~31,SIMD floating point registers

Modes AArch32

User Application
FIQ Fast Interrupt
IRQ Interrupt
Supervisor Operating System
Abort Prefetch abort of instructiion/data
Undefined After undefined instruction
System Privileged user mode (for OS functions)
Monitor On TrustZone Platforms

Modes on Aarch64

EL0 Unprivileged,applications(with task protection,etc)
EL1 Operating system,kernel,etc
EL2 Hypervisor(for virtualisation)
EL3 Secure monitor(for switching to/from secure state)

svc,hvc,smc指令切换，对EL1~3有三种不同的中断向量，客户端可以生产virtual exceptions

CP15 is no more

Cache,address and TLB management now have dedicated instructions

Memory management

Execpt for EL0,all exception levels have their own memory translation

context(EL0 is managed by EL1)

This means up to 3 stage translation depending on the context